International Journal of Electronic Devices and Networking
2020, Vol. 1, Issue 1, Part A
Comparative analysis of low power 8T SRAM
Author(s): Nishant Malik
Abstract: There is requirement for a higher noise tolerant and low power static random access memory (SRAM) in today’s market. A stable 8 transistors SRAM (8T SRAM) cell is presented in this paper for low power operation. The presented SRAM cell has a structure similar to standard 6 transistors SRAM (6T SRAM) with additional 2 buffer transistors and a complementary word line. Additional buffer transistors are added to ensure low leakage power due to stacking effect. Parametric comparison with standard 6T SRAM is done in this paper. Design metrics such as read static noise margin (RSNM), write trip voltage (WTV) and leakage power are compared. The proposed cell dropped leakage power 85% of the standard 6T SRAM cell.
Pages: 22-27 | Views: 1093 | Downloads: 680
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How to cite this article:
Nishant Malik. Comparative analysis of low power 8T SRAM. Int J Electron Devices Networking 2020;1(1):22-27.