International Journal of Electronic Devices and Networking
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P-ISSN: 2708-4477, E-ISSN: 2708-4485

International Journal of Electronic Devices and Networking


2021, Vol. 2, Issue 1, Part A
Phase measurement technique for Synchronous devices in FPGA using XOR gates


Author(s): Muthulakshmi KA, Kavya C and Vinthiya R

Abstract: Every Electronic system use PLL (Phase Locked Loop) that requires a clock signal and applications like clock and data recovery circuits for serial input output and RF transceivers, Analog to Digital Converter Spectrum analyzer, image processing, smart grid and radar. In our project we use Bang Bang phase detector i.e.) binary phase detector which has potential of use in high speed which can be implemented with a simple D flip flop and XOR gate. We also discussed the procedure of the phase measurement system, the calibration sequence involved, followed by the performance of the design in terms of timing issues i.e. skew and jitter using XOR gates to make this phase detector suitable for FPGA where there is a need to preserve the synchronous relationship between the clocks.

Pages: 45-50 | Views: 923 | Downloads: 480

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International Journal of Electronic Devices and Networking
How to cite this article:
Muthulakshmi KA, Kavya C, Vinthiya R. Phase measurement technique for Synchronous devices in FPGA using XOR gates. Int J Electron Devices Networking 2021;2(1):45-50.
International Journal of Electronic Devices and Networking
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