International Journal of Electronic Devices and Networking
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P-ISSN: 2708-4477, E-ISSN: 2708-4485

International Journal of Electronic Devices and Networking


2021, Vol. 2, Issue 2, Part A
Design of an efficient adders for signal processing applications


Author(s): G Aswini, G Gajalakshmi, JN Jayashree and R Kousalya ME

Abstract: An adder is a digital circuit that simply performs addition of numbers. In many Personal computers and different kinds of processors, adders are deployed in the arithmetic and logical units or ALU. They are additionally utilized in different pieces of the processor, where they are employed to compute addresses, indices of tables, incrementation and decrementing process in operators and similar operations in the hardware. Error Tolerant Adder (ETA) is a kind of adder which sacrifice its accuracy to improve its speed and area. The power delay product is the average product of power consumed and worst-case delay is improved. By lessening the power consumed, the battery life of any portable device can be improved. This project presents the design of high speed and area efficient adders which include Ripple carry adder (RCA), Carry look ahead adder (CLA), Carry skip adder (CSA), Kogge stone adder, Brent Kung adder each incorporated with the Error tolerant adder (ETA) and compared the speed, area power utilized by each adder with and without incorporating ETA. The results are tabulated to show the variation in speed, area and power for different adders.

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International Journal of Electronic Devices and Networking
How to cite this article:
G Aswini, G Gajalakshmi, JN Jayashree, R Kousalya ME. Design of an efficient adders for signal processing applications. Int J Electron Devices Networking 2021;2(2):01-05.
International Journal of Electronic Devices and Networking
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