International Journal of Electronic Devices and Networking
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P-ISSN: 2708-4477, E-ISSN: 2708-4485

International Journal of Electronic Devices and Networking


2023, Vol. 4, Issue 1, Part A
Design and simulation of asynchronous FIFO buffer using globally asynchronous and locally synchronous methodology


Author(s): Abhinav Ark, Aakansha Kumari, Surabhi Dutta, Sweta Kumari and Megha Dadel

Abstract: Combining a faster system with a slower system might be difficult. To solve this issue, FIFO buffers are used. A FIFO buffer is called the First In, First Out buffer. The initial written data will be read from this non-random access memory type. Two systems that operate at distinct frequency levels are linked using a FIFO buffer. The high-frequency component is connected to the low-frequency component through a FIFO Buffer with a particular operating frequency to prevent data loss during transmission. This research paper uses globally asynchronous and locally synchronous method to build a FIFO Buffer and improve performance.

Pages: 52-57 | Views: 272 | Downloads: 93

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International Journal of Electronic Devices and Networking
How to cite this article:
Abhinav Ark, Aakansha Kumari, Surabhi Dutta, Sweta Kumari, Megha Dadel. Design and simulation of asynchronous FIFO buffer using globally asynchronous and locally synchronous methodology. Int J Electron Devices Networking 2023;4(1):52-57.
International Journal of Electronic Devices and Networking
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