International Journal of Electronic Devices and Networking
2025, Vol. 6, Issue 2, Part A
Design and implementation of 6T SRAM cells using cadence virtuoso
Author(s): Maheboob Baig and Shilpa KC
Abstract: This paper presents the design and analysis of a low-power 6-transistor (6T) Static Random Access Memory (SRAM) cell using 180nm CMOS technology in the Cadence Virtuoso environment. The objective is to achieve functional stability, minimal power consumption, and an optimized layout suitable for academic and embedded applications. Reliable read/write operations are ensured by proper transistor sizing and structural optimization. Performance evaluation, via transient and DC simulations, highlights write/read behavior, signal integrity, and power efficiency. The butterfly curve method estimates the Static Noise Margin (SNM). Layout verification is performed using Design Rule Check (DRC), Layout Versus Schematic (LVS), and parasitic extraction. Results confirm the suitability of the 180nm process for low-power SRAM with a balanced trade-off between stability, area, and efficiency. Voltage swing and internal node behavior are examined to ensure logic retention. This study demonstrates the practical relevance of 180nm technology for memory design and academic research.
DOI: 10.22271/27084477.2025.v6.i2a.77
Pages: 07-12 | Views: 412 | Downloads: 278
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How to cite this article:
Maheboob Baig, Shilpa KC. Design and implementation of 6T SRAM cells using cadence virtuoso. Int J Electron Devices Networking 2025;6(2):07-12. DOI: 10.22271/27084477.2025.v6.i2a.77
